The present invention relates generally to data signal acquisition systems, and in particular to digital data signal sampling systems with two different sampling clock signals of unrelated frequencies or sampling timebases, including time correlation signal generation means for identifying the last previous clock pulse, and data reconstruction means for reconstructing the sampled digital data signals in proper time relationship for display on a cathode ray tube or other suitable display device.
The digital signal sampling system of the present invention is especially useful in a logic analyzer instrument, but is also useful in other digital signal measurement instruments such as digital oscilloscopes. In a logic analyzer the same or two different digital data signals are sampled simultaneously by two sampling clock signals which may be of different timebases. In order to reconstruct the sampled data signals in their original real time relationship when sampling with two different timebases, it has been proposed to synthesize a common synchronous clock signal from the two different sampling clock signals. Such a common clock signal will, under most conditions, enable proper sampling for data acquisition from both digital data signals. However, this is not true under all conditions and has the disadvantage that it produces large quantities of irrelevant sampled data which must be sorted through to find the relevant sampled data, thereby requiring large memory storage capability which is expensive and inefficient.
Another technique is employed in U.S. Pat. No. 4,425,643 issued to David D. Chapman and Gerd H. Hoern entitled "Multi-Speed Logic Analyzer" to provide a logic analyzer with two different sampling timebases for measuring the same or two different digital data input signals including a high frequency and a low frequency sampling clock signal. The low frequency clock is stored and transmitted as a time reference to the computer for reconstruction of the sampled data signals. However, the high frequency clock signals must be maintained at least twice the frequency of the low frequency clock signals during sampling for accurate reconstruction of the sampled data signals in their correct real time relationship. Thus, if the frequency of the sampling clock signals changes during sampling so that the high frequency clock signal becomes lower in frequency than the low frequency clock signal, inaccuracies are produced in the reconstructed digital data signal using such logic analyzer system.
The digital signal sampling system of the present invention overcomes these disadvantages by employing a time correlation circuit which produces two time correlation signals of different binary levels to indicate the last previous clock pulse received thereby in response to the application of two store clock signals derived from the two sampling clock signals of different unrelated timebases. These time correlation signals are stored in the acquisition memories along with the sampled data, to indicate by their binary logic levels the time relationship of the clock pulses in first and second store clock signals and the first and second sampling clock signals. Thus, the first time correlation signal has a binary "1" level if there is a clock pulse of the second store clock signal between the current and previous clock pulses of the first store clock signal, and has a "0" level if there is no clock pulse of the second store clock signal between the current and previous clock pulses of the first store clock signal. Similarly, the second time correlation signal has a "1" level if there is a clock pulse of the first store clock signal between the current and previous clock pulses of the second store clock signal, and has a "0" level if there is is no clock pulse of the first store clock signal between the current and previous clock pulses of the second store clock signal. These first and second correlation signals together with the corresponding first and second digital data sample signals are stored in first and second acquisition memories when the store clock pulses are applied to such memories. The stored data signals and correlation signals are read out of the memory and together with a last clock pulse output of the correlation circuit are applied to a data signal reconstruction such as a digital computer which is programmed to reconstruct from such signals the sampled digital data signals in proper real time relationship and to display the reconstructed signals on a cathode ray tube or other display device.